Library ieee;
use ieee.std_logic_1164.all;
entity av04 is
port(reset,iclk:in std_logic; idata: in std_logic_vector(7 downto 0);
oclk: out std_logic; odata: out std_logic_vector(7 downto 0));
end av04;
architecture whtodo of av04 is
type statetype is(st0,st1,st2,st3);
signal currentstate,nextstate:statetype;
begin
process(currentstate)
variable akdata:std_logic vector(7 downto 0);
begin
case currentstate is
when st0 =>
akdata<= idata;oclk<= '0';nextstate<= st1;
when st1 =>
akdata<= idata +akdata;nextstate<= st2;
when st2 =>
akdata<= idata +akdata;nextstate<= st3;
when st3 =>
akdata<= idata +akdata;
akdata<="00"&akdata(7 downto 2);
oclk<='1';
odata<= akdata;nextstate<= st0;
end case;
end process;
process(reset,iclk)
begin
if(reset ='1')then currentstate<= st0;
elsif(iclk'event and iclk = '1')then currentstate<= nextstate;
endif;
end process;
end wbtodo;