题目内容
（请给出正确答案）
[主观题]
在空格中填写正确的数据module decoder_using_case （） 4’h0 : decoder_out = 16’h0001;
在空格中填写正确的数据module decoder_using_case （） 4’h0 : decoder_out = 16’h0001; 4’h1 : decoder_out = 16’h0002; 4’h2 : decoder_out = 16’h0004; 4’h3 : decoder_out = 16’h0008; 4’h4 : decoder_out = 16’h0010; 4’h5 : decoder_out = 16’h0020; 4’h6 : decoder_out = 16’h0040; 4’h7 : decoder_out = 16’h0080; 4’h8 : decoder_out = 16’h ; 4’h9 : decoder_out = 16’h0200; 4’hA : decoder_out = 16’h0400; 4’hB : decoder_out = 16’h0800; 4’hC : decoder_out = 16’h1000; 4’hD : decoder_out = 16’h2000; 4’hE : decoder_out = 16’h4000; 4’hF : decoder_out = 16’h8000; endcase end endendmodule
提问人：网友squalia
发布时间：2022-01-07
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请在下划线处填写正确的代码： module reduce (clk, reset, in, out); input clk, reset, in; output out; parameter S0 = 2’b00; parameter S1 = 2’b01; parameter S2 = 2’b10; reg out; reg [1:0] state; reg [1:0] next_state; always @(posedge clk) if (reset) state = S0; e lse state = next_state; always @(in or state) case (state) …… …… S2: begin if (in) next_state = ; else next_state = S0 ; end …… ……
请在下划线处填写正确的代码： module reduce (clk, reset, in, out); input clk, reset, in; output out; parameter S0 = 2’b00; parameter S1 = 2’b01; parameter S2 = 2’b10; reg out; reg [1:0] state; reg [1:0] next_state; always @(posedge clk) if (reset) state = S0; e lse state = next_state; always @(in or state) case (state) …… …… S1: begin if (in) next_state = S2; else next_state = ; end …… ……
