Problem in this exercise assume that the logic blo...

Problem in this exercise assume that the logic blocks used to implement a processor’s complete datapath have the following latencies:“Register read” is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. “Register setup” is the amount of time a register’s data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File. Q1: What is the latency of an R-type instruction？ ____ ps (number only )