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For conditions in question 4. Q6: What is the minimum clock period for this CPU？ ____ ps （number only )
提问人：网友yongyuandi
发布时间：2022-01-07
题目内容
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更多“For conditions in question 4. …”相关的问题
第1题
For conditions in question 4. Q3: What is the latency of sw instruction? ____ ps ( number only )
第2题
For conditions in question 7. Q2: When execute jalr instruction, the control signals PCSel, ImmSel, ASel, BSel, RegWEn, and WBSel generated by the controller are respectively ( ).
A、1, J, 0, 1, 1, 2
B、1, I, 0, 1, 0, 2
C、1, I, 0, 1, 1, 2
D、1, J, 0, 1, 1, 1
第3题
For the following single-cycle datapath, answer the questions: 
When silicon chips are fabricated, defects in materials and manufacturing errors can result in defective circuits. A very common defect is for one signal wire to get "broken" and always register a logical 0. This is often called a "stuck-at-0" fault. Q1: Which instructions fail to operate correctly if the ASel wire is stuck at 0?
When silicon chips are fabricated, defects in materials and manufacturing errors can result in defective circuits. A very common defect is for one signal wire to get "broken" and always register a logical 0. This is often called a "stuck-at-0" fault. Q1: Which instructions fail to operate correctly if the ASel wire is stuck at 0?
A、B-Format
B、I-Format
C、J-Format
D、U-Format
第4题
For conditions in question 1. Q2: Which instructions fail to operate correctly if the RegWEn wire is stuck at 0?
A、R-Format
B、I-Format
C、J-Format
D、U-Format
第5题
For conditions in question 4. Q3: The fastest frequency you could clock this single-cycle datapath is _____GHz.
第6题
For conditions in question 4. Q2: The total time needed to execute beq instruction is _____ps.
第7题
Assume the delay for each stage in the single-cycle datapath is as follows: IF ID EX MEM WB 200ps 100ps 200ps 200ps 100ps Q1: The total time needed to execute ori instruction is _____ps.
第8题
For conditions in question 1. Q2: If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split to improve the performance of the processor?
A、IF
B、ID
C、EX
D、MEM
第9题
For conditions in question 7. Q2: There is a control hazard between instructions 4 and 5. (True or False)
第10题
Assuming the individual stages of the datapath have the following latencies: IF ID EX MEM WB 250ps 350ps 150ps 300ps 200ps Q1: What is the clock cycle time in a pipelined processor? _____ps
